From 357ba1ab0f08ee0a0653a3cde8db246f5c10447f Mon Sep 17 00:00:00 2001
From: leoshusar <husar.leos@outlook.com>
Date: Mon, 16 Oct 2023 00:29:13 +0200
Subject: [PATCH] Change UART source clock to `UART_SCLK_DEFAULT` when IDF >=v5
 (#5533)

---
 esphome/components/uart/uart_component_esp_idf.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/esphome/components/uart/uart_component_esp_idf.cpp b/esphome/components/uart/uart_component_esp_idf.cpp
index ae772fa8f8..9b519c4568 100644
--- a/esphome/components/uart/uart_component_esp_idf.cpp
+++ b/esphome/components/uart/uart_component_esp_idf.cpp
@@ -48,7 +48,11 @@ uart_config_t IDFUARTComponent::get_config_() {
   uart_config.parity = parity;
   uart_config.stop_bits = this->stop_bits_ == 1 ? UART_STOP_BITS_1 : UART_STOP_BITS_2;
   uart_config.flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 0, 0)
+  uart_config.source_clk = UART_SCLK_DEFAULT;
+#else
   uart_config.source_clk = UART_SCLK_APB;
+#endif
   uart_config.rx_flow_ctrl_thresh = 122;
 
   return uart_config;