Home-IoT/esphome
1
0
Fork 0
mirror of https://github.com/esphome/esphome.git synced 2024-11-27 09:18:00 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 6

Fix bug in ook avg reg, reserved bit should be 1

Browse source
This commit is contained in:
Jonathan Swoboda 2024-11-10 18:31:29 -05:00
parent f5e7c339b6
commit 79dea478f2
2 changed files with 8 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
esphome/components/sx127x/sx127x.cpp
View file

@ -191,7 +191,7 @@ void SX127x::configure() {
// config sync generation and setup ook threshold // config sync generation and setup ook threshold
uint8_t bitsync = this->bitsync_ ? BIT_SYNC_ON : BIT_SYNC_OFF; uint8_t bitsync = this->bitsync_ ? BIT_SYNC_ON : BIT_SYNC_OFF;
this->write_register_(REG_OOK_PEAK, bitsync | OOK_THRESH_STEP_0_5 | OOK_THRESH_PEAK); this->write_register_(REG_OOK_PEAK, bitsync | OOK_THRESH_STEP_0_5 | OOK_THRESH_PEAK);
this->write_register_(REG_OOK_AVG, OOK_THRESH_DEC_1_8); this->write_register_(REG_OOK_AVG, OOK_AVG_RESERVED | OOK_THRESH_DEC_1_8);
// set rx floor // set rx floor
this->write_register_(REG_OOK_FIX, 256 + int(this->rx_floor_ * 2.0)); this->write_register_(REG_OOK_FIX, 256 + int(this->rx_floor_ * 2.0));

13
esphome/components/sx127x/sx127x.h
View file

@ -47,7 +47,7 @@ enum SX127xReg : uint8_t {
REG_FIFO_THRESH = 0x35, REG_FIFO_THRESH = 0x35,
REG_DIO_MAPPING1 = 0x40, REG_DIO_MAPPING1 = 0x40,
REG_DIO_MAPPING2 = 0x41, REG_DIO_MAPPING2 = 0x41,
REG_VERSION = 0x42 REG_VERSION = 0x42,
}; };
enum SX127xRxConfig : uint8_t { enum SX127xRxConfig : uint8_t {
@ -89,7 +89,7 @@ enum SX127xOpMode : uint8_t {
MODE_TX = 0x03, MODE_TX = 0x03,
MODE_TX_FS = 0x02, MODE_TX_FS = 0x02,
MODE_STDBY = 0x01, MODE_STDBY = 0x01,
MODE_SLEEP = 0x00 MODE_SLEEP = 0x00,
}; };
enum SX127xDioMapping1 : uint8_t { enum SX127xDioMapping1 : uint8_t {
@ -134,7 +134,7 @@ enum SX127xOokPeak : uint8_t {
OOK_THRESH_STEP_2_0 = 0x03, OOK_THRESH_STEP_2_0 = 0x03,
OOK_THRESH_STEP_1_5 = 0x02, OOK_THRESH_STEP_1_5 = 0x02,
OOK_THRESH_STEP_1_0 = 0x01, OOK_THRESH_STEP_1_0 = 0x01,
OOK_THRESH_STEP_0_5 = 0x00 OOK_THRESH_STEP_0_5 = 0x00,
}; };
enum SX127xOokAvg : uint8_t { enum SX127xOokAvg : uint8_t {
@ -145,7 +145,8 @@ enum SX127xOokAvg : uint8_t {
OOK_THRESH_DEC_1_8 = 0x60, OOK_THRESH_DEC_1_8 = 0x60,
OOK_THRESH_DEC_1_4 = 0x40, OOK_THRESH_DEC_1_4 = 0x40,
OOK_THRESH_DEC_1_2 = 0x20, OOK_THRESH_DEC_1_2 = 0x20,
OOK_THRESH_DEC_1 = 0x00 OOK_THRESH_DEC_1 = 0x00,
OOK_AVG_RESERVED = 0x10,
}; };
enum SX127xPacketConfig2 : uint8_t { enum SX127xPacketConfig2 : uint8_t {
@ -174,7 +175,7 @@ enum SX127xRxBw : uint8_t {
RX_BW_125_0 = 0x02, RX_BW_125_0 = 0x02,
RX_BW_166_7 = 0x11, RX_BW_166_7 = 0x11,
RX_BW_200_0 = 0x09, RX_BW_200_0 = 0x09,
RX_BW_250_0 = 0x01 RX_BW_250_0 = 0x01,
}; };
enum SX127xPaRamp : uint8_t { enum SX127xPaRamp : uint8_t {
@ -200,7 +201,7 @@ enum SX127xPaRamp : uint8_t {
PA_RAMP_500 = 0x03, PA_RAMP_500 = 0x03,
PA_RAMP_1000 = 0x02, PA_RAMP_1000 = 0x02,
PA_RAMP_2000 = 0x01, PA_RAMP_2000 = 0x01,
PA_RAMP_3400 = 0x00 PA_RAMP_3400 = 0x00,
}; };
struct SX127xStore { struct SX127xStore {