diff --git a/esphome/components/ethernet/ethernet_component.cpp b/esphome/components/ethernet/ethernet_component.cpp
index 17093ffb3d..3af462d593 100644
--- a/esphome/components/ethernet/ethernet_component.cpp
+++ b/esphome/components/ethernet/ethernet_component.cpp
@@ -184,6 +184,10 @@ void EthernetComponent::setup() {
     // KSZ8081RNA default is incorrect. It expects a 25MHz clock instead of the 50MHz we provide.
     this->ksz8081_set_clock_reference_(mac);
   }
+  if (this->type_ == ETHERNET_TYPE_RTL8201 && this->clk_mode_ == EMAC_CLK_EXT_IN) {
+    // Change in default behavior of RTL8201FI may require register setting to enable external clock
+    this->rtl8201_set_rmii_mode_(mac);
+  }
 #endif
 
   // use ESP internal eth mac
@@ -583,6 +587,46 @@ void EthernetComponent::ksz8081_set_clock_reference_(esp_eth_mac_t *mac) {
     ESP_LOGVV(TAG, "KSZ8081 PHY Control 2: %s", format_hex_pretty((u_int8_t *) &phy_control_2, 2).c_str());
   }
 }
+constexpr uint8_t RTL8201_RMSR_REG_ADDR = 0x10;
+void EthernetComponent::rtl8201_set_rmii_mode_(esp_eth_mac_t *mac) {
+  esp_err_t err;
+  uint32_t phy_rmii_mode;
+  err = mac->write_phy_reg(mac, this->phy_addr_, 0x1f, 0x07);
+  ESPHL_ERROR_CHECK(err, "Setting Page 7 failed");
+
+  /*
+   * RTL8201 RMII Mode Setting Register (RMSR)
+   * Page 7 Register 16
+   *
+   * bit 0      Reserved            0
+   * bit 1      Rg_rmii_rxdsel      1 (default)
+   * bit 2      Rg_rmii_rxdv_sel:   0 (default)
+   * bit 3      RMII Mode:          1 (RMII Mode)
+   * bit 4~7    Rg_rmii_rx_offset:  1111 (default)
+   * bit 8~11   Rg_rmii_tx_offset:  1111 (default)
+   * bit 12     Rg_rmii_clkdir:     1 (Input)
+   * bit 13~15  Reserved            000
+   *
+   * Binary: 0001 1111 1111 1010
+   * Hex: 0x1FFA
+   *
+   */
+
+  err = mac->read_phy_reg(mac, this->phy_addr_, RTL8201_RMSR_REG_ADDR, &(phy_rmii_mode));
+  ESPHL_ERROR_CHECK(err, "Read PHY RMSR Register failed");
+  ESP_LOGV(TAG, "Hardware default RTL8201 RMII Mode Register is: 0x%04X", phy_rmii_mode);
+
+  err = mac->write_phy_reg(mac, this->phy_addr_, RTL8201_RMSR_REG_ADDR, 0x1FFA);
+  ESPHL_ERROR_CHECK(err, "Setting Register 16 RMII Mode Setting failed");
+
+  err = mac->read_phy_reg(mac, this->phy_addr_, RTL8201_RMSR_REG_ADDR, &(phy_rmii_mode));
+  ESPHL_ERROR_CHECK(err, "Read PHY RMSR Register failed");
+  ESP_LOGV(TAG, "Setting RTL8201 RMII Mode Register to: 0x%04X", phy_rmii_mode);
+
+  err = mac->write_phy_reg(mac, this->phy_addr_, 0x1f, 0x0);
+  ESPHL_ERROR_CHECK(err, "Setting Page 0 failed");
+}
+
 #endif
 
 }  // namespace ethernet
diff --git a/esphome/components/ethernet/ethernet_component.h b/esphome/components/ethernet/ethernet_component.h
index daeb5a2029..6276885fd1 100644
--- a/esphome/components/ethernet/ethernet_component.h
+++ b/esphome/components/ethernet/ethernet_component.h
@@ -86,6 +86,8 @@ class EthernetComponent : public Component {
   void dump_connect_params_();
   /// @brief Set `RMII Reference Clock Select` bit for KSZ8081.
   void ksz8081_set_clock_reference_(esp_eth_mac_t *mac);
+  /// @brief Set `RMII Mode Setting Register` for RTL8201.
+  void rtl8201_set_rmii_mode_(esp_eth_mac_t *mac);
 
   std::string use_address_;
 #ifdef USE_ETHERNET_SPI