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SPI: Revert clk_pin to standard output pin schema (#6368)
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parent
c4f4d25041
commit
e33e09a685
2 changed files with 4 additions and 16 deletions
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@ -29,7 +29,6 @@ from esphome.const import (
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PLATFORM_ESP32,
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PLATFORM_ESP8266,
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PLATFORM_RP2040,
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CONF_ALLOW_OTHER_USES,
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CONF_DATA_PINS,
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)
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from esphome.core import (
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@ -199,8 +198,6 @@ def get_hw_spi(config, available):
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def validate_spi_config(config):
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available = list(range(len(get_hw_interface_list())))
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for spi in config:
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# map pin number to schema
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spi[CONF_CLK_PIN] = pins.gpio_output_pin_schema(spi[CONF_CLK_PIN])
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interface = spi[CONF_INTERFACE]
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if interface == "software":
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pass
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@ -257,21 +254,11 @@ def get_spi_interface(index):
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return "new SPIClass(HSPI)"
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# Do not use a pin schema for the number, as that will trigger a pin reuse error due to duplication of the
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# clock pin in the standard and quad schemas.
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clk_pin_validator = cv.maybe_simple_value(
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{
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cv.Required(CONF_NUMBER): cv.Any(cv.int_, cv.string),
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cv.Optional(CONF_ALLOW_OTHER_USES): cv.boolean,
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},
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key=CONF_NUMBER,
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)
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SPI_SCHEMA = cv.All(
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cv.Schema(
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{
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cv.GenerateID(): cv.declare_id(SPIComponent),
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cv.Required(CONF_CLK_PIN): clk_pin_validator,
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cv.Required(CONF_CLK_PIN): pins.gpio_output_pin_schema,
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cv.Optional(CONF_MISO_PIN): pins.gpio_input_pin_schema,
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cv.Optional(CONF_MOSI_PIN): pins.gpio_output_pin_schema,
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cv.Optional(CONF_FORCE_SW): cv.invalid(
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@ -291,7 +278,7 @@ SPI_QUAD_SCHEMA = cv.All(
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cv.Schema(
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{
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cv.GenerateID(): cv.declare_id(QuadSPIComponent),
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cv.Required(CONF_CLK_PIN): clk_pin_validator,
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cv.Required(CONF_CLK_PIN): pins.gpio_output_pin_schema,
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cv.Required(CONF_DATA_PINS): cv.All(
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cv.ensure_list(pins.internal_gpio_output_pin_number),
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cv.Length(min=4, max=4),
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@ -2,7 +2,8 @@ spi:
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- id: spi_id_1
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type: single
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clk_pin:
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number: GPIO7
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number: GPIO0
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ignore_strapping_warning: true
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allow_other_uses: false
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mosi_pin: GPIO6
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interface: hardware
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