From f34e797a0d9baa7ad8df082226322140f0a07b68 Mon Sep 17 00:00:00 2001 From: Jesse Hills <3060199+jesserockz@users.noreply.github.com> Date: Wed, 7 Dec 2022 07:23:07 +1300 Subject: [PATCH] Change 4 chip limit on sn74hc595 to 256 (#4108) --- esphome/components/sn74hc595/__init__.py | 14 +++++------ esphome/components/sn74hc595/sn74hc595.cpp | 29 +++++++++------------- esphome/components/sn74hc595/sn74hc595.h | 23 +++++++++-------- 3 files changed, 32 insertions(+), 34 deletions(-) diff --git a/esphome/components/sn74hc595/__init__.py b/esphome/components/sn74hc595/__init__.py index 630abc8bca..92b6d8d0e5 100644 --- a/esphome/components/sn74hc595/__init__.py +++ b/esphome/components/sn74hc595/__init__.py @@ -17,7 +17,9 @@ MULTI_CONF = True sn74hc595_ns = cg.esphome_ns.namespace("sn74hc595") SN74HC595Component = sn74hc595_ns.class_("SN74HC595Component", cg.Component) -SN74HC595GPIOPin = sn74hc595_ns.class_("SN74HC595GPIOPin", cg.GPIOPin) +SN74HC595GPIOPin = sn74hc595_ns.class_( + "SN74HC595GPIOPin", cg.GPIOPin, cg.Parented.template(SN74HC595Component) +) CONF_SN74HC595 = "sn74hc595" CONF_LATCH_PIN = "latch_pin" @@ -30,7 +32,7 @@ CONFIG_SCHEMA = cv.Schema( cv.Required(CONF_CLOCK_PIN): pins.gpio_output_pin_schema, cv.Required(CONF_LATCH_PIN): pins.gpio_output_pin_schema, cv.Optional(CONF_OE_PIN): pins.gpio_output_pin_schema, - cv.Optional(CONF_SR_COUNT, default=1): cv.int_range(1, 4), + cv.Optional(CONF_SR_COUNT, default=1): cv.int_range(min=1, max=256), } ).extend(cv.COMPONENT_SCHEMA) @@ -60,7 +62,7 @@ SN74HC595_PIN_SCHEMA = cv.All( { cv.GenerateID(): cv.declare_id(SN74HC595GPIOPin), cv.Required(CONF_SN74HC595): cv.use_id(SN74HC595Component), - cv.Required(CONF_NUMBER): cv.int_range(min=0, max=31), + cv.Required(CONF_NUMBER): cv.int_range(min=0, max=2048, max_included=False), cv.Optional(CONF_MODE, default={}): cv.All( { cv.Optional(CONF_OUTPUT, default=True): cv.All( @@ -76,10 +78,8 @@ SN74HC595_PIN_SCHEMA = cv.All( @pins.PIN_SCHEMA_REGISTRY.register(CONF_SN74HC595, SN74HC595_PIN_SCHEMA) async def sn74hc595_pin_to_code(config): var = cg.new_Pvariable(config[CONF_ID]) - parent = await cg.get_variable(config[CONF_SN74HC595]) - cg.add(var.set_parent(parent)) + await cg.register_parented(var, config[CONF_SN74HC595]) - num = config[CONF_NUMBER] - cg.add(var.set_pin(num)) + cg.add(var.set_pin(config[CONF_NUMBER])) cg.add(var.set_inverted(config[CONF_INVERTED])) return var diff --git a/esphome/components/sn74hc595/sn74hc595.cpp b/esphome/components/sn74hc595/sn74hc595.cpp index 5ebf50e5cb..1895b1d5a6 100644 --- a/esphome/components/sn74hc595/sn74hc595.cpp +++ b/esphome/components/sn74hc595/sn74hc595.cpp @@ -28,24 +28,21 @@ void SN74HC595Component::setup() { void SN74HC595Component::dump_config() { ESP_LOGCONFIG(TAG, "SN74HC595:"); } -bool SN74HC595Component::digital_read_(uint8_t pin) { return this->output_bits_ >> pin; } - -void SN74HC595Component::digital_write_(uint8_t pin, bool value) { - uint32_t mask = 1UL << pin; - this->output_bits_ &= ~mask; - if (value) - this->output_bits_ |= mask; +void SN74HC595Component::digital_write_(uint16_t pin, bool value) { + if (pin >= this->sr_count_ * 8) { + ESP_LOGE(TAG, "Pin %u is out of range! Maximum pin number with %u chips in series is %u", pin, this->sr_count_, + (this->sr_count_ * 8) - 1); + return; + } + this->output_bits_[pin] = value; this->write_gpio_(); } -bool SN74HC595Component::write_gpio_() { - for (int i = this->sr_count_ - 1; i >= 0; i--) { - uint8_t data = (uint8_t)(this->output_bits_ >> (8 * i) & 0xff); - for (int j = 0; j < 8; j++) { - this->data_pin_->digital_write(data & (1 << (7 - j))); - this->clock_pin_->digital_write(true); - this->clock_pin_->digital_write(false); - } +void SN74HC595Component::write_gpio_() { + for (auto bit = this->output_bits_.rbegin(); bit != this->output_bits_.rend(); bit++) { + this->data_pin_->digital_write(*bit); + this->clock_pin_->digital_write(true); + this->clock_pin_->digital_write(false); } // pulse latch to activate new values @@ -56,8 +53,6 @@ bool SN74HC595Component::write_gpio_() { if (this->have_oe_pin_) { this->oe_pin_->digital_write(false); } - - return true; } float SN74HC595Component::get_setup_priority() const { return setup_priority::IO; } diff --git a/esphome/components/sn74hc595/sn74hc595.h b/esphome/components/sn74hc595/sn74hc595.h index 784019c3a6..64bf06d881 100644 --- a/esphome/components/sn74hc595/sn74hc595.h +++ b/esphome/components/sn74hc595/sn74hc595.h @@ -2,6 +2,9 @@ #include "esphome/core/component.h" #include "esphome/core/hal.h" +#include "esphome/core/helpers.h" + +#include namespace esphome { namespace sn74hc595 { @@ -21,13 +24,15 @@ class SN74HC595Component : public Component { oe_pin_ = pin; have_oe_pin_ = true; } - void set_sr_count(uint8_t count) { sr_count_ = count; } + void set_sr_count(uint8_t count) { + sr_count_ = count; + this->output_bits_.resize(count * 8); + } protected: friend class SN74HC595GPIOPin; - bool digital_read_(uint8_t pin); - void digital_write_(uint8_t pin, bool value); - bool write_gpio_(); + void digital_write_(uint16_t pin, bool value); + void write_gpio_(); GPIOPin *data_pin_; GPIOPin *clock_pin_; @@ -35,11 +40,11 @@ class SN74HC595Component : public Component { GPIOPin *oe_pin_; uint8_t sr_count_; bool have_oe_pin_{false}; - uint32_t output_bits_{0x00}; + std::vector output_bits_; }; /// Helper class to expose a SC74HC595 pin as an internal output GPIO pin. -class SN74HC595GPIOPin : public GPIOPin { +class SN74HC595GPIOPin : public GPIOPin, public Parented { public: void setup() override {} void pin_mode(gpio::Flags flags) override {} @@ -47,13 +52,11 @@ class SN74HC595GPIOPin : public GPIOPin { void digital_write(bool value) override; std::string dump_summary() const override; - void set_parent(SN74HC595Component *parent) { parent_ = parent; } - void set_pin(uint8_t pin) { pin_ = pin; } + void set_pin(uint16_t pin) { pin_ = pin; } void set_inverted(bool inverted) { inverted_ = inverted; } protected: - SN74HC595Component *parent_; - uint8_t pin_; + uint16_t pin_; bool inverted_; };